(1) Field of the Invention
The invention relates to processes for the manufacture of semiconductor devices and more particularly to processes for forming self-aligned polysilicon gate field effect transistors with dual thickness thin gate oxides.
(2) Description of Prior Art and Background to the Invention
Complimentary metal oxide semiconductor(CMOS) field effect transistor(FET) technology involves the formation n-channel FETs(NMOS) and p-channel FETs(PMOS) in combination to form low current, high performance integrated circuits. The complimentary use of NMOS and PMOS devices, typically in the form of a basic inverter device, allows a considerable increase of circuit density of circuit elements by reduction of heat generation. The increase in device density accompanied by the shrinkage of device size has resulted in improved circuit performance and reliability as well as reduced cost. For these reasons CMOS integrated circuits have found widespread use, particularly in digital applications.
The basic MOSFET, whether it be NMOS or PMOS is typically formed by a self-aligned polysilicon gate process. An region of active silicon region surface for the device is defined on a silicon wafer by an opening surrounded by field oxide isolation(FOX). A gate oxide is then grown on the exposed silicon regions and a polysilicon gate electrode is patterned over the gate oxide. Source and drain regions are next formed in the active region, typically by ion implantation. The device is completed by depositing an insulative layer over the wafer and forming contacts to the source/drain regions and to the gate electrode through openings in the insulative layer.
The performance of the MOSFET is inversely proportional to the gate oxide thickness. Efforts to enhance performance as well as reduce power consumption have driven gate oxide thicknesses to well below 100 Angstroms. It was originally predicted that the physical limit of gate oxide thickness is somewhere around 30 .ANG. because below this thickness carriers are removed by direct tunneling, faster than they can be supplied by thermal generation (Wolf, S., "Silicon Processing for the VLSI Era", Vol.3, Lattice Press, Sunset Beach, Calif., (1995), p438). However, recent studies by Bell Laboratories scientists now predict that the physical limit is of the order of 5 atoms which translates to about 14 .ANG. for an SiO.sub.2 dielectric.
MOSFET devices are currently being developed which have gate oxide thicknesses as low as 20 .ANG.. As one might expect, serious new problems arise when the technology is driven to such levels requiring the invention of new methods to deal with them. Although some of these problems may not be generally soluble with today's technology, it is prudent to selectively exploit situations where the effects of these problems are minimal. It turns out that some devices are more susceptible to degradation than others. For example boron doped gate electrodes on p-channel devices are likely to degrade the channel region by emitting dopant across a thin oxide whereas this problem is much less likely to occur with arsenic doped gate electrodes on n-channel devices. These differences have led to the recent development of integrated circuits with dual oxide thicknesses. Thus, in a CMOS integrated circuit, the performance of the n-channel devices can be improved by selectively providing them with thinner gate oxides than the p-channel gate oxide thicker.
With regard to circuit device application, it is desirable to have a relatively thick gate oxide under the gates of the cell access transistors in a DRAM array to reduce wordline capacitance, while the performance of peripheral devices which drive the array would benefit from a relatively thin gate oxide. Such an application is cited by Gonzalez, U.S. Pat. No. 5,863,819. Growing two different gate oxide thicknesses is a challenge in itself. Typically, as in Gonzalez, the thicker oxide is grown first. Then a photomask is applied and the thicker oxide is etched away with aqueous HF from the gate regions where the thinner oxide is required. The mask is then stripped and the thinner oxide is grown.
A problem with this procedure is that a thin layer of native oxide forms on the silicon surface during a non-HF stripping and cleaning processes which remove the photoresist. An initial layer of about 10 .ANG. thick continues to grow to a saturation thickness of about 16 to 18 .ANG.. The native oxide is of poor structural quality and contains impurities. In the instance of Gonzalez a 10 .ANG. native oxide is only about 10% of the total thin oxide. However, if left in place during the formation of a 20 .ANG. thin gate oxide, the 10 .ANG. of poor quality native oxide would comprise about half of the total. Obviously, a gate insulator with such a large poor quality portion would show degraded performance of the MOSFET. It would therefore be desirable to have a method for reducing, as much as possible, the native oxide from the silicon surfaces in the thin oxide device regions without damaging the already grown thicker gate oxide regions.
Beguwala, et.al., U.S. Pat. No. 4,277,320 in a process for direct thermal nitridation of silicon, shows the removal of a native oxide film in a chamber with ultrapure H.sub.2 or with a dilute HF atmosphere. After oxide removal, a low pressure atmosphere of ionized N.sub.2 or NH.sub.3 is used to form a silicon nitride film. The native oxide removal and the thermal nitridation are sequentially performed in-situ within the same chamber. Thus there is no exposure of the fresh silicon surface to atmosphere prior to coverage by a nitride film.
Chau, et.al., U.S. Pat. No. 5,244,843 shows a method for forming a 60-80 .ANG. gate oxides and controlling the formation of a native oxide by pushing the rack of wafers into the oxidation furnace at a controlled rate with N.sub.2 flow. The native oxide layer is deliberately grown first so that it protects the silicon from chlorine attack during the subsequent gate oxidation wherein TCA (trichloroethane) is added to the oxidizing gas flow. Webb, et.al., U.S. Pat. No. 5,228,950 show a method for removing silicon rich oxide residues and polysilicon stringers by a high pressure NF.sub.3 plasma etch. NF.sub.3 is very corrosive and also attacks silicon.